FPGA Notes

My Collection

• Nexys Video
• Kria #1
• Kria #2

RISC-V implementation

Implementations in the following languages:

• Python
• C
• VHDL (for GHDL)
• VHDL (for Vivado)

RISC-V mini OS

Required hardware:

• Serial-out
• Serial-in
• Ethernet-out
• Ethernet-in
• Reference clock in (without automatic switching)

Features:

• Character-based I/O
• Monitor program
• PLL programming
• TCP/IP implementation
• SCPI implementation

RISC-V toolchain

What do we want to be able to do:

• (C): working simple programs.
• (C): printf() based I/O.
• (C): dynamic memory management.
• (C++) working simple programs.
• (C++) iostreams based I/O.
• (C++) dynamic memory management
• (C++) STL
• (C++) working exceptions

What we need:

• GCC (compiler, assembler, linker) that supports the rv32i target and ilp32 ABI.
• A C library for my target (newlib, most probably).
• A linker script for my target.
• A crt0.s implementation for our target.